Cypress Semiconductor CY62148ESL Specification Sheet

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CY62148ESL MoBL
®
4-Mbit (512K x 8) Static RAM
Cypress Semiconductor Corporation 198 Champion Court San Jose
,
CA 95134-1709 408-943-2600
Document #: 001-50045 Rev. ** Revised January 21, 2009
Features
Very high speed: 55 ns
Wide voltage range: 2.2V to 3.6V
and 4.5V to 5.5V
Ultra low standby power
Typical standby current: 1 μA
Maximum standby current: 7 μA
Ultra low active power
Typical active current: 2 mA at f = 1 MHz
Easy memory expansion with CE and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Available in Pb-free 32-pin STSOP package
Functional Description
The CY62148ESL is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE
HIGH). The eight input and output pins (IO
0
through IO
7
) are
placed in a high impedance state when the device is deselected
(CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE
LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE
) inputs LOW. Data on the eight IO pins (IO
0
through IO
7
) is
then written into the location specified on the address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE
) and Output
Enable (OE
) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the IO pins.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A
13
A
14
A
15
A
16
A
17
ROW DECODER
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A
10
A
11
A
12
A
18
Logic Block Diagram
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