Cypress Semiconductor CY7C1443AV33 Specification Sheet

Download Specification sheet of Cypress Semiconductor CY7C1441AV33 Computer Hardware for Free or View it Online on All-Guides.com.

Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 1
1
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 2
2
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 3
3
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 4
4
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 5
5
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 6
6
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 7
7
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 8
8
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 9
9
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 10
10
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 11
11
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 12
12
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 13
13
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 14
14
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 15
15
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 16
16
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 17
17
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 18
18
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 19
19
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 20
20
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 21
21
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 22
22
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 23
23
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 24
24
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 25
25
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 26
26
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 27
27
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 28
28
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 29
29
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 30
30
Cypress Semiconductor CY7C1441AV33 Specification sheet - Page 31
31
36-Mbit (1M x 36/2M x 18/512K x 72)
Flow-Through SRAM
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-05357 Rev. *G Revised May 09, 2008
Features
Supports 133-MHz bus operations
1M x 36/2M x 18/512K x 72 common IO
3.3V core power supply
2.5V or 3.3V IO power supply
Fast clock-to-output times
6.5 ns (133-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
CY7C1441AV33, CY7C1443AV33 available in
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and
non-lead-free 165-ball FBGA package. CY7C1447AV33
available in Pb-free and non-lead-free 209-ball FBGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode option
Functional Description
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
[1]
are
3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE
1
), depth-expansion Chip Enables (CE
2
and
CE
3
), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BW
x
, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE
) and the ZZ
pin.
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst sequence,
while a LOW selects a linear burst sequence. Burst accesses
can be initiated with the Processor Address Strobe (ADSP
) or the
cache Controller Address Strobe (ADSC
) inputs. Address
advancement is controlled by the Address Advancement (ADV
)
input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
) or Address
Strobe Controller (ADSC
) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV
).
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.
Selection Guide
Description 133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 310 290 mA
Maximum CMOS Standby Current 120 120 mA
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
[+] Feedback