HP E1340A User's Manual
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STATus
The STATus subsystem controls the SCPI-defined Operation and
Questionable Signal Status Registers. Each is comprised of a Condition
Register, an Event Register, an enable mask, and negative and positive
transition filters.
Each Status Register works as follows: when a condition occurs, the
appropriate bit in the Condition Register is set or cleared. If the the
corresponding transition filter is enabled for that bit, the same bit is set in
the associated Event Register. The contents of the Event Register and the
enable mask are logically ANDed bit-for-bit; if any bit of the result is set,
the summary bit for that register is set in the status byte. The status byte
summary bit for the Operation Status Register is bit 7; for the Questionable
Signal Status Register, bit 3.
Operation Status
Register
Only bits 0 (CALibrating), 3 (SWEeping), and 8 (INITiated) are defined for
the HP E1340A. All other bits are always zero.
Bit 0 - CALibrating: Set (1) during calibration. Cleared (0)
otherwise.
Bit 3 - SWEeping: Set (1) while a frequency sweep or list is in
progress. Cleared (0) when waveform generation is halted, when
frequency sweeping or lists are not selected, and at the end of each
sweep or list.
Bit 8 - INITiated: Set (1) by the INITiate:IMMediate command.
Cleared (0) by the
ABORt command. When outputting a single
burst of waveform repetitions (
ARM:LAYer2:COUNt 1 set and
ARM:LAYer1:COUNt not set to INFinity), it is also cleared by any
other command executed after waveform generation completes.
Questionable Signal
Status Register
All bits are always 0. This register is implemented only for SCPI
compatibility purposes.
Subsystem Syntax STATus
:OPERation|QUEStionable
:CONDition? [query only]
:ENABle <
unmask>
[:EVENt]? [query only]
:NTRansition <
unmask>
:PTRansition <
unmask>
:PRESet [no query]
STATus[:LEVel][:IMMediate]:OFFSet
Chapter 7 HP E1340A Command Reference 181