CADENCE DESIGN SYSTEMS CADENCE INCYTE CHIP ESTIMATOR Datasheet

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DATASHEET
Cadence
®
InCyte Chip Estimator is a unique coupling of
software and an IP ecosystem that enables rapid and accu-
rate early chip planning. Fastwhat-if” estimation of size,
performance, power, and cost enables early exploration of
functional content, IP components, memories, and process
technology with foresight into the technical and business
consequences of these decisions. InCyte Chip Estimator
helps chip design projects start and stay on track toward
their technical and business goals.
CADENCE INCYTE CHIP
ESTIMATOR
With the escalating costs of chip design,
it is imperative that projects begin with
careful planning to ensure that goals
can be met and monitored for progress.
Cadence InCyte Chip Estimator combines
breakthrough size, performance, and
power estimation algorithms with the
industry’s largest collection of IP to enable
accurate what-if analysis that explores
both technical and business feasibility.
Closing early on a system-on-chip (SoC)
specification that meets project goals
and gaining insight into downstream
technical implementation reduces overall
project risk and speeds the project’s time
to market. InCyte Chip Estimators fast,
accurate, and simple-to-use environment
helps any user achieve optimal results
without being an IC design expert. It can
be used by technology team members
(design architects, chip integrators,
Design Specification
Blocks, Gate Counts
Clocks, Constraints
Memory, IP, I/Os
IP Catalog Data
User-Defined IP
Estimation Results
Die Area
Power
Performance
Early Floorplan
Packaged Chip Cost
Customizable Reports
EDA Tool Input Data
Technology
Models
Figure 1: Size, performance, and power estimation algorithms combined with an extensive IP catalog enable early
and accurate what-if analysis
design leads, engineering management)
as well as business team members (field
sales consultants, technical marketing,
IC component procurement, RFQ
response, executive management) to plan,
estimate, and track chip design projects.
This is useful for fabless semiconductor
companies, integrated device manufac-
turers, ASIC vendors and customers,
design services providers, and IP providers.