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CADENCE DESIGN SYSTEMS CADENCE LITHO ELECTRICAL ANALYZER Datasheet

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DATASHEET

Electrical DFM Analysis and Optimization

Cadence

®

Litho Electrical Analyzer is a complete and

silicon-correlated electrical DFM analyzer that allows

designers to optimize and control the impact of lithography,

mask, etch, RET, OPC, and CMP effects on chip parameters.

Its contour-based analysis technology provides an accurate,

model-based solution for designers to minimize the impact

of manufacturing variations on design performance.

CADENCE LITHO

ELECTRICAL ANALYZER

CADENCE LITHO

ELECTRICAL ANALYZER

Cadence Litho Electrical Analyzer allows

designers using sub-90nm processes to

identify and analyze parametric issues

associated with manufacturing variability

and to minimize their effect on chip

performance—all within their existing

flows for IP, custom analog, and cell-

based digital design.

Cadence Litho Electrical Analyzer uses

fab-certified technology to predict

contours across the process window

and to predict device and interconnect

silicon electrical behavior. It gets its

silicon-accurate critical dimensions (CD)

from Cadence Litho Physical Analyzer,

which delivers accurate full-chip contour

shape predictions in a matter of hours.

Cadence device and interconnect models

for accurate prediction of silicon electrical

behavior have already been validated

in silicon at several semiconductor

manufacturers.

Figure 1: Principles of Cadence Litho Electrical Analyzer