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CADENCE DESIGN SYSTEMS CADENCE RF SIP METHODOLOGY KIT Datasheet

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OVERVIEW

The Cadence

®

RF SiP Methodology Kit accelerates the application of EDA

technologies to system-in-package (SiP) designs for Radio Frequency

(RF) and wireless applications. It provides methodologies that maximize

design productivity and predictability for customers leveraging the

advantages of SiP technology. An integrated set of products built around

proven methodologies enables complete front-to-back SiP design and

implementation. All this is demonstrated on a segment representative

design, resulting in reduced time to new products, increased functional

densities, and higher system performance.

CADENCE RF SIP METHODOLOGY KIT

The Cadence RF SiP Methodology Kit leverages new SiP

technologies and verified advanced methodologies for RF SiP

design. It enables wireless design teams to achieve predictable

design schedules by boosting design productivity while also

increasing the likelihood of first-pass success by improving

quality. By combining comprehensive links between system

design, physical implementation and manufacturing, the kit

allows full-SiP electrical analysis and characterization of critical

paths as well as behavioral modeling from overall system-level

simulation through bottom-up verification.

These capabilities are demonstrated on a segment representative

design (an 802.11b/g WLAN RF SiP) that includes a Helic-based

RF transceiver and analog baseband die in a 180nm generic

CMOS process, a second AMS analog front-end baseband

interface die in a 90nm generic CMOS process, and embedded

and discrete passive off-chip components in a generic LTCC

substrate. The kit also contains re-usable, pre-configured

components from test-benches, models, and simulation plans for

block and full SiP-level verification and physical implementation

approaches. Additionally, design teams are led through a step-

by-step example on how to apply advanced Cadence

technologies to best achieve design success.

CADENCE RF SIP

METHODOLOGY KIT

CADENCE SIP DESIGN TECHNOLOGY

Manufacturers of high-performance consumer electronics are

turning to SiP design because it can provide a number of

advantages over just SoC. In addition to reduced cost, lower

power, and higher performance, SiP design offers the flexibility

to mix radio RF and high-speed digital circuitry in the same

package. However, this also means it requires expert engineering

talent in widely divergent fields. Conventional EDA solutions

have failed to automate the design processes required for

efficient SiP development. By enabling and integrating design

concept exploration, capture, construction, optimization, and

validation of complex multi-chip and discrete substrate

assemblies on printed circuit boards (PCBs), the Cadence SiP

design technology streamlines the integration of multiple high-

pin-count chips onto a single substrate. This approach allows

companies to adopt what were once expert engineering SiP

design capabilities for mainstream product development.

Cadence SiP solutions seamlessly integrate into Cadence

Encounter

®

for die abstract codesign, Cadence Virtuoso

®

for

RF module design, and Cadence Allegro

®

for package/board

co-design.