CADENCE DESIGN SYSTEMS CADENCE SIP DIGITAL DESIGN Datasheet

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DATASHEET
Cadence technology for digital
SiP design includes three
focused products for full SiP
implementation:
• Cadence SiP Digital Architect
XL and GXL
• Cadence SiP Digital Layout GXL
• Cadence SiP Digital SI XL
CADENCE SIP
DIGITAL CO-DESIGN
TECHNOLOGY
Manufacturers of high-performance
consumer electronics are turning to SiP
design because it can provide a number
of significant advantages such as increased
functional density, integration of disparate
chip technologies, low power, improved
signal performance/integrity and ease of
integration into PCB system. However, this
also means it requires expert engineering
talent in widely divergent fields, which,
to date, has limited mainstream adoption.
By streamlining the integration of multiple
high-pin-count chips onto a single substrate
through a concurrent connectivity driven
co-design methodology, the Cadence SiP
digital co-design technology allows
companies to adopt what were once
expert engineering SiP design capabilities
for mainstream product development.
Cadence SiP solutions seamlessly integrate
into Cadence Encounter
®
technology for
die abstract co-design, Cadence Virtuoso
®
technology for RF module design, and
Cadence Allegro
®
technology for package/
board co-design. (See Figure 1.)
A COMPLETE
CONNECTIVITY DRIVEN
CO-DESIGN SOLUTION
The Cadence digital-driven SiP flow focuses
on the design challenges of integrating
multiple large high-pin-count chips onto
a single substrate. This flow targets the
major challenges of SiP level connectivity
definition and management, physical
concept prototyping of the SiP floorplan,
including multi-chip die stacks, and die
I/O planning to optimize and minimize
substrate connectivity routing and signal
integrity challenges. This flow is driven
by Encounter and Verilog
®
connectivity.
CADENCE SiP DIGITAL DESIGN
System-in-package (SiP) implementation poses new hurdles
for system architects and designers. Conventional EDA
solutions have failed to automate the design processes
required for efficient SiP development. By enabling and
integrating design concept exploration, capture, construction,
optimization, and validation of complex multi-chip and discrete
substrate assemblies on printed circuit boards (PCBs), the
Cadence SiP design technology streamlines the integration
of multiple high-pin-count chips onto a single substrate.