CADENCE DESIGN SYSTEMS SOC ENCOUNTER RTL-TO-GDSII SYSTEM Datasheet

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DATASHEET
The Cadence
®
SoC Encounter
RTL-to-GDSII System
supports large-scale complexat and hierarchical designs.
Itcombines advanced RTL and physical synthesis, silicon
virtual prototyping, automatedoorplan synthesis, clock
tree and clock mesh synthesis, advanced nanometer routing,
mixed-signal support, advanced low-power implementation,
and a complete suite of design for manufacturability,
variation, and yield optimization technologies required for
advanced node designs. These and other capabilities deliver
the highest quality of silicon (QoS) for timing, signal integrity,
area, power, and yield, including integrated statistical-based
analyses and optimization.
SOC ENCOUNTER RTL-TO-GDSII SYSTEM
SOC ENCOUNTER
RTL-TO-GDSII SYSTEM
The SoC Encounter System combines
RTL synthesis, silicon virtual prototyping,
design planning, and full-chip digital
implementation in a single system, and
has been enhanced to support today’s
high-performance advanced node designs.
Engineers can synthesize, physically
implement, and optimize a flat virtual
prototype—with the benefit of actual
routed interconnect—giving designers an
early, accurate view of design feasibility.
Once feasibility is established, designers
can immediately progress to full-scale
implementation without ever having
to leave the environment. The SoC
Encounter System enables the utmost
in manufacturing predictability and
advanced timing closure using native
signoff analysis engines delivering the
best QoS.
BENEFITS
• Silicon-provensystemhandlesatand
hierarchical 100M+ gate designs
• CombinesthepowerofRTLsynthesis,
silicon virtual prototyping, physical
synthesis, full-chip design implemen-
tation, and final signoff analysis in a
single unified environment
• Dramaticallyincreasesproductivity
with an integrated, high-performance,
high-capacity design solution to address
large-scale, complex chips
• Enablesrapiddesignexploration
and accurate chip feasibility analysis,
including an automated floorplan
synthesis and ranking system for
aflexible and predictable path to
designclosure
• Providesaexiblesolutiontoaddress
the latest low-power advanced node
and mixed-signal design requirements
• Offersintegratedandconsistent
process variation analysis and
optimization, including multi-mode,
multi-corner (MMMC) and statistical
intra-die, die-to-die, wafer-to-wafer,
and random variation support utilizing
industry-standard statistical ECSM
library models and characterization
• Bringssignicantproductivitygains
through signoff-driven implemen-
tation, and intuitive and visual global
timing, power, and clock debug and
diagnosticsfeatures
• Enablesconcurrentdesignand
optimization, of chip and package
with integrated automatic area
andperipheral I/O placement
and optimization, including
RDLroutingcapabilities